From ec319c9ec0acc975fcdfbfa2e378b82c9be9ab0a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 30 Aug 2020 14:03:40 +0100 Subject: Add RTLBlock intermediate language --- src/extraction/Extraction.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/extraction') diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index b1a885e..e6ee512 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -16,7 +16,11 @@ * along with this program. If not, see . *) -From vericert Require Verilog Value Compiler. +From vericert Require + Verilog + Value + Compiler + RTLBlockgen. From Coq Require DecidableClass. @@ -162,12 +166,15 @@ Extract Inlined Constant Binary.B2R => "fun _ -> assert false". Extract Inlined Constant Binary.round_mode => "fun _ -> assert false". Extract Inlined Constant Bracket.inbetween_loc => "fun _ -> assert false". +Extract Constant RTLBlockgen.partition => "Partition.partition". + (* Needed in Coq 8.4 to avoid problems with Function definitions. *) Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction Verilog.module Value.uvalueToZ vericert.Compiler.transf_hls + RTLBlockgen.transl_program Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state -- cgit