From f470234beafacccf743a75d4d0e6213b8861ca30 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 12 Jun 2020 11:37:22 +0100 Subject: Remove extraction of simulator --- src/extraction/Extraction.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/extraction') diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 0028fcb..ba87af6 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -16,7 +16,7 @@ * along with this program. If not, see . *) -From coqup Require Verilog Value Compiler Simulator. +From coqup Require Verilog Value Compiler. From Coq Require DecidableClass. @@ -166,7 +166,7 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction - Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Simulator.simulate + Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state -- cgit