From ed97c6d4edeac9cab96be17b74ef02373ed36888 Mon Sep 17 00:00:00 2001 From: Michalis Pardalos Date: Fri, 30 Apr 2021 16:08:09 +0100 Subject: Tie all modules' clock to main --- src/hls/HTL.v | 1 + 1 file changed, 1 insertion(+) (limited to 'src/hls/HTL.v') diff --git a/src/hls/HTL.v b/src/hls/HTL.v index 4f00c79..8474878 100644 --- a/src/hls/HTL.v +++ b/src/hls/HTL.v @@ -59,6 +59,7 @@ Inductive controlsignal : Type := | ctrl_return : controlsignal | ctrl_start : controlsignal | ctrl_reset : controlsignal + | ctrl_clk : controlsignal | ctrl_param (idx : nat) : controlsignal. Definition controlsignal_sz (s : controlsignal) : nat := -- cgit