From 2837868fcc427b2161b083f33d3de495f0c21bf7 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 31 Mar 2021 20:45:15 +0100 Subject: Add memory disable --- src/hls/PrintVerilog.ml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/hls/PrintVerilog.ml') diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index d076386..61f5b5e 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -164,11 +164,14 @@ let decl i = function let pprint_module_item i = function | Vdeclaration d -> decl i d | Valways (e, s) -> - concat [indent i; "always "; pprint_edge_top i e; "\n"; pprint_stmnt (i+1) s] + concat [indent i; "always "; pprint_edge_top i e; "begin\n"; + pprint_stmnt (i+1) s; indent i; "end\n"] | Valways_ff (e, s) -> - concat [indent i; "always "; pprint_edge_top i e; "\n"; pprint_stmnt (i+1) s] + concat [indent i; "always "; pprint_edge_top i e; "begin\n"; + pprint_stmnt (i+1) s; indent i; "end\n"] | Valways_comb (e, s) -> - concat [indent i; "always "; pprint_edge_top i e; "\n"; pprint_stmnt (i+1) s] + concat [indent i; "always "; pprint_edge_top i e; "begin\n"; + pprint_stmnt (i+1) s; indent i; "end\n"] let rec intersperse c = function | [] -> [] -- cgit