From d6cfa2f23ddbc83340386c3111f33740ea0cbdeb Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Mar 2021 10:26:45 +0000 Subject: Print Verilog in reverse order --- src/hls/PrintVerilog.ml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/hls/PrintVerilog.ml') diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 3817fd3..d076386 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -247,7 +247,7 @@ let pprint_module debug i n m = ]; concat [ indent i; "module "; (extern_atom n); "("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n"; - fold_map (pprint_module_item (i+1)) m.mod_body; + fold_map (pprint_module_item (i+1)) (List.rev m.mod_body); if !option_initial then print_initial i (Nat.to_int m.mod_stk_len) m.mod_stk else ""; if debug then debug_always_verbose i m.mod_clk m.mod_st else ""; indent i; "endmodule\n\n" -- cgit