From f3a0c5c0095258159c495d70fda6749bbf89de70 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Feb 2021 20:34:20 +0000 Subject: Add predicated values and instructions --- src/hls/PrintVerilog.ml | 1 + 1 file changed, 1 insertion(+) (limited to 'src/hls/PrintVerilog.ml') diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 4a6c165..b2633ec 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -87,6 +87,7 @@ let rec pprint_expr = function | Vunop (u, e) -> concat ["("; unop u; pprint_expr e; ")"] | Vbinop (op, a, b) -> concat [pprint_binop (pprint_expr a) (pprint_expr b) op] | Vternary (c, t, f) -> concat ["("; pprint_expr c; " ? "; pprint_expr t; " : "; pprint_expr f; ")"] + | Vrange (r, e1, e2) -> concat [register r; "["; pprint_expr e1; ":"; pprint_expr e2; "]"] let rec pprint_stmnt i = let pprint_case (e, s) = concat [ indent (i + 1); pprint_expr e; ": begin\n"; pprint_stmnt (i + 2) s; -- cgit