From dc518898cac3b8e06684b6e66377d430ab30a52e Mon Sep 17 00:00:00 2001 From: Michalis Pardalos Date: Mon, 1 Mar 2021 11:16:33 +0000 Subject: Typos in Veriloggen --- src/hls/Veriloggen.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/hls/Veriloggen.v') diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index 83f7abe..2ced686 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -112,7 +112,7 @@ Section RENUMBER. ret (Vbinop op e1' e2') | Vunop op e => do e' <- renumber_expr e; - ret (Vunop op e) + ret (Vunop op e') | Vternary e1 e2 e3 => do e1' <- renumber_expr e1; do e2' <- renumber_expr e2; @@ -122,7 +122,7 @@ Section RENUMBER. do e1' <- renumber_expr e1; do e2' <- renumber_expr e2; do r' <- renumber_reg r; - ret (Vrange r e1 e2) + ret (Vrange r e1' e2') end. Fixpoint renumber_stmnt (stmnt : Verilog.stmnt) := -- cgit