From bbc5bd889c5d4520140406bd5dd4a397d0d2c975 Mon Sep 17 00:00:00 2001
From: James Pollard <james@pollard.dev>
Date: Mon, 25 May 2020 18:20:23 +0100
Subject: Start work on array support

Try to add a verilog register to represent the stack.
---
 src/translation/Veriloggen.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/translation/Veriloggen.v')

diff --git a/src/translation/Veriloggen.v b/src/translation/Veriloggen.v
index 6aa94df..0d846a5 100644
--- a/src/translation/Veriloggen.v
+++ b/src/translation/Veriloggen.v
@@ -551,6 +551,7 @@ Definition set_int_size (r: reg) : reg * nat := (r, 32%nat).
 Definition transf_module (f: function) : mon module :=
   do fin <- decl_io 1%nat;
   do rtrn <- decl_io 32%nat;
+  do _ <- decl_fresh_reg ((Z.to_nat f.(fn_stacksize)) * 8%nat);
   do _ <- traverselist (transf_instr (fst fin) (fst rtrn)) (Maps.PTree.elements f.(fn_code));
   do start <- decl_io 1%nat;
   do rst <- decl_io 1%nat;
-- 
cgit