From 5cf10a4c70763cbb95747b19ac35b57a9dee4dd5 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 24 Jul 2020 10:22:13 +0100 Subject: More renames to get it to compile --- src/verilog/PrintVerilog.mli | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/verilog/PrintVerilog.mli') diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 47af3ef..6a15ee9 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -18,8 +18,8 @@ val pprint_stmnt : int -> Verilog.stmnt -> string -val print_value : out_channel -> Value.value -> unit +val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit -val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit +val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit -- cgit