From c02c4c9c4f1e4529526676e5e6aca2b44dd4584c Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 22 Jun 2020 09:47:18 +0100 Subject: Add print for debug always block in module --- src/verilog/PrintVerilog.mli | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/verilog/PrintVerilog.mli') diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 0df9d06..6544e52 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -18,6 +18,6 @@ val print_value : out_channel -> Value.value -> unit -val print_program : out_channel -> Verilog.program -> unit +val print_program : bool -> out_channel -> Verilog.program -> unit val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit -- cgit