From 43f766ea8aff8309d94173cc1e2670eb8ddce68f Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 20 May 2020 10:51:14 +0100
Subject: Switch position of empty rule

---
 src/verilog/Verilog.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/verilog/Verilog.v')

diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v
index c0bce25..c1e0a79 100644
--- a/src/verilog/Verilog.v
+++ b/src/verilog/Verilog.v
@@ -244,14 +244,14 @@ Inductive expr_runp : fext -> assocmap -> expr -> value -> Prop :=
   | erun_Vlit :
       forall fext assoc v,
       expr_runp fext assoc (Vlit v) v
-  | erun_Vvar_empty :
-      forall fext assoc r sz,
-      assoc!r = None ->
-      expr_runp fext assoc (Vvar r) (ZToValue sz 0)
   | erun_Vvar :
       forall fext assoc v r,
       assoc!r = Some v ->
       expr_runp fext assoc (Vvar r) v
+  | erun_Vvar_empty :
+      forall fext assoc r sz,
+      assoc!r = None ->
+      expr_runp fext assoc (Vvar r) (ZToValue sz 0)
   | erun_Vinputvar :
       forall fext assoc r v,
       fext!r = Some v ->
-- 
cgit