From 5cfa4af9c6e4d9703e3142c24ae78c7da0ac575f Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 4 May 2020 16:13:16 +0100 Subject: Add equality check for value --- src/verilog/Verilog.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/verilog/Verilog.v') diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index a927eac..756dc12 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -1,4 +1,4 @@ -(* -*- mode: coq -*- +(* * CoqUp: Verified high-level synthesis. * Copyright (C) 2019-2020 Yann Herklotz * -- cgit