From b71b75aa7f9e4db0575b01cf25b7ad6dd88abff4 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 4 Jun 2020 20:03:10 +0100 Subject: Finished main proof with small assumptions --- src/verilog/Verilog.v | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src/verilog/Verilog.v') diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index ce7ddd9..cccdf9a 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -32,7 +32,8 @@ From compcert Require Integers Events. From compcert Require Import Errors Smallstep Globalenvs. Import HexNotationValue. -Import AssocMapNotation. + +Local Open Scope assocmap. Definition reg : Type := positive. Definition node : Type := positive. @@ -246,12 +247,8 @@ Inductive expr_runp : fext -> assocmap -> expr -> value -> Prop := expr_runp fext assoc (Vlit v) v | erun_Vvar : forall fext assoc v r, - assoc!r = Some v -> + assoc#r = v -> expr_runp fext assoc (Vvar r) v - | erun_Vvar_empty : - forall fext assoc r sz, - assoc!r = None -> - expr_runp fext assoc (Vvar r) (ZToValue sz 0) | erun_Vinputvar : forall fext assoc r v, fext!r = Some v -> -- cgit