From ef2fef6a290797f90c52a8a8706b7a5163cdb499 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 17 Apr 2020 21:16:58 +0100 Subject: Fix Verilog.v --- src/verilog/Verilog.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/verilog/Verilog.v') diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index c1c68ba..61df580 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -419,7 +419,7 @@ Definition module_run (n : nat) (m : module) : res assoclist := Local Close Scope error_monad_scope. -Theorem value_eq_size_if_eq: +(*Theorem value_eq_size_if_eq: forall lv rv EQ, vsize lv = vsize rv -> value_eq_size lv rv = left EQ. Proof. intros. unfold value_eq_size. -- cgit