From 50ec2fb12454c2bc1f902c955f0b81df71b58c39 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 26 Jun 2020 09:40:16 +0100 Subject: Fix Verilog semantics and fix order of always blocks --- src/verilog/Verilog.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/verilog') diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index d476710..555ddbd 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -712,7 +712,7 @@ Definition empty_stack (m : module) : assocmap_arr := Inductive step : genv -> state -> Events.trace -> state -> Prop := | step_module : - forall asr asa asr' asa' basr1 nasr1 basa1 nasa1 f stval pstval m sf st g, + forall asr asa asr' asa' basr1 nasr1 basa1 nasa1 f stval pstval m sf st g ist, asr!(m.(mod_st)) = Some ist -> valueToPos ist = st -> mis_stepp f (mkassociations asr empty_assocmap) -- cgit