From e3c66ff88570c5370b37f51404f71f485d2e5dfe Mon Sep 17 00:00:00 2001 From: James Pollard Date: Wed, 3 Jun 2020 17:31:35 +0100 Subject: HTLgenspec status in line with develop --- src/verilog/HTL.v | 1 + 1 file changed, 1 insertion(+) (limited to 'src/verilog') diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index a553453..cb081b2 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -43,6 +43,7 @@ Record module: Type := mod_controllogic : controllogic; mod_entrypoint : node; mod_st : reg; + mod_stk : reg; mod_finish : reg; mod_return : reg }. -- cgit