From 6e290b7049fc874c32e62ab816493dc5200ebc4e Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 18 Feb 2020 12:08:15 +0000 Subject: Update Verilog AST with flat array --- src/Extraction/Extraction.v | 4 ++++ src/Verilog/VerilogAST.v | 3 +++ 2 files changed, 7 insertions(+) (limited to 'src') diff --git a/src/Extraction/Extraction.v b/src/Extraction/Extraction.v index 1db8e3c..01b03d1 100644 --- a/src/Extraction/Extraction.v +++ b/src/Extraction/Extraction.v @@ -18,9 +18,13 @@ Require CoqUp.Verilog.VerilogAST. +(* Standard lib *) Require Import ExtrOcamlBasic. Require Import ExtrOcamlString. +(* Avoid name clashes *) +Extraction Blacklist List String Int. + Cd "src/Extraction". Separate Extraction VerilogAST.nat_to_value VerilogAST.value_to_nat VerilogAST.verilog VerilogAST.verilog_example. diff --git a/src/Verilog/VerilogAST.v b/src/Verilog/VerilogAST.v index 362fe45..5886652 100644 --- a/src/Verilog/VerilogAST.v +++ b/src/Verilog/VerilogAST.v @@ -32,6 +32,9 @@ Inductive value : Type := | VBool (b : bool) | VArray (l : list value). +Inductive literal : Type := +| LitArray (l : list bool). + Definition cons_value (a b : value) : value := match a, b with | VBool _, VArray b' => VArray (a :: b') -- cgit