From ef205f12c75891be73d221995946df441d143791 Mon Sep 17 00:00:00 2001 From: Michalis Pardalos Date: Sun, 28 Feb 2021 22:00:57 +0000 Subject: Unset finish signal on reset --- src/hls/Veriloggen.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index a7a8c2a..83f7abe 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -337,7 +337,9 @@ Section TRANSLATE. let body : list Verilog.module_item:= Valways (Vposedge (HTL.mod_clk m)) (Vcond (Vbinop Veq (Vvar (HTL.mod_reset m)) (Vlit (ZToValue 1))) - (Vnonblock (Vvar (HTL.mod_st m)) (Vlit (posToValue (HTL.mod_entrypoint m)))) + (Vseq + (Vnonblock (Vvar (HTL.mod_st m)) (Vlit (posToValue (HTL.mod_entrypoint m)))) + (Vnonblock (Vvar (HTL.mod_finish m)) (Vlit (ZToValue 0)))) (Vcase (Vvar (HTL.mod_st m)) case_el_ctrl (Some Vskip))) :: Valways (Vposedge (HTL.mod_clk m)) (Vcase (Vvar (HTL.mod_st m)) case_el_data (Some Vskip)) :: List.map Vdeclaration (arr_to_Vdeclarr (AssocMap.elements (HTL.mod_arrdecls m)) -- cgit