From 0ac7a07f5320dfe3372821c41269f1da1b3ba6c8 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Tue, 14 May 2019 18:46:18 +0100
Subject: Optimisations in the generation

---
 src/VeriFuzz/Verilog/Gen.hs | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 0cff33a..96a90f9 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -347,20 +347,18 @@ statement = do
     where onDepth c n = if c ^. stmntDepth > 0 then n else 0
 
 alwaysSeq :: StateGen ModItem
-alwaysSeq = do
-    stat <- seqBlock
-    return $ Always (EventCtrl (EPosEdge "clk") (Just stat))
+alwaysSeq = Always . EventCtrl (EPosEdge "clk") . Just <$> seqBlock
 
 instantiate :: ModDecl -> StateGen ModItem
 instantiate (ModDecl i outP inP _ _) = do
     context <- get
-    outs    <-
-        fmap (Id . view portName) <$> (replicateM (length outP) $ nextPort Wire)
+    outs    <- fmap (Id . view portName)
+        <$> replicateM (length outP) (nextPort Wire)
     ins <-
         (Id "clk" :)
         .   fmap (Id . view portName)
         .   take (length inP - 1)
-        <$> (Hog.shuffle $ context ^. variables)
+        <$> Hog.shuffle (context ^. variables)
     ident <- makeIdentifier "modinst"
     Hog.choice
         [ return . ModInst i ident $ ModConn <$> outs <> ins
-- 
cgit