From 12778f69e296f31660775c68ed016d5a693644d3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 14 Nov 2019 17:41:23 +0000
Subject: Update bug

---
 bugs/quartus_12.md | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/bugs/quartus_12.md b/bugs/quartus_12.md
index 9d8b278..24469ce 100644
--- a/bugs/quartus_12.md
+++ b/bugs/quartus_12.md
@@ -17,3 +17,13 @@ module top(y, wire1);
   assign y = 2'b11 ^ $signed(wire1);
 endmodule
 ```
+
+When Quartus is passed the following design instead, it does output the right result which is `2'b10`.
+
+```verilog
+module top(y, wire1);
+  output [1:0] y;
+  input signed wire1;
+  assign y = 2'b11 ^ wire1;
+endmodule
+```
-- 
cgit