From 2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sun, 30 Dec 2018 12:03:35 +0100
Subject: [Fix #14] Add size to Port type

---
 src/Test/VeriFuzz/Graph/ASTGen.hs    |  4 ++--
 src/Test/VeriFuzz/Verilog/AST.hs     | 16 ++++++++++------
 src/Test/VeriFuzz/Verilog/Helpers.hs | 12 ++++++------
 src/Test/VeriFuzz/Verilog/Mutate.hs  |  5 +++++
 4 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 00eb71d..cf996de 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -44,7 +44,7 @@ genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
 genPortsAST f c =
   (port . frNode <$> f c)
   where
-    port = Port $ PortNet Wire
+    port = Port (PortNet Wire) 1
 
 -- | Generates the nested expression AST, so that it can then generate the
 -- assignment expressions.
@@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items
   where
     id = Identifier "gen_module"
     ports = genPortsAST inputsC c
-    output = Just $ Port (PortNet Wire) "y"
+    output = Just $ Port (PortNet Wire) 1 "y"
     items = genAssignAST c
 
 generateAST :: Circuit -> VerilogSrc
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 4c3649d..65be816 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -146,6 +146,7 @@ data PortType = PortNet Net
 
 -- | Port declaration.
 data Port = Port { _portType :: PortType
+                 , _portSize :: Int
                  , _portName :: Identifier
                  } deriving (Show, Eq, Ord)
 
@@ -208,6 +209,9 @@ newtype VerilogSrc = VerilogSrc { _getVerilogSrc :: [Description] }
 
 -- Generate Arbitrary instances for the AST
 
+positiveArb :: (QC.Arbitrary a, Ord a, Num a) => QC.Gen a
+positiveArb = QC.suchThat QC.arbitrary (>0)
+
 expr :: Int -> QC.Gen Expression
 expr 0 = QC.oneof
   [ PrimExpr <$> QC.arbitrary
@@ -250,8 +254,8 @@ statement n
 
 modPortGen :: QC.Gen Port
 modPortGen = QC.oneof
-  [ Port (PortNet Wire) <$> QC.arbitrary
-  , Port <$> (Reg <$> QC.arbitrary) <*> QC.arbitrary
+  [ Port (PortNet Wire) <$> positiveArb <*> QC.arbitrary
+  , Port <$> (Reg <$> QC.arbitrary) <*> positiveArb <*> QC.arbitrary
   ]
 
 instance QC.Arbitrary Text where
@@ -263,7 +267,7 @@ instance QC.Arbitrary Identifier where
     Identifier . T.pack <$> replicateM l (QC.elements ['a'..'z'])
 
 instance QC.Arbitrary Number where
-  arbitrary = Number <$> QC.suchThat QC.arbitrary (>0) <*> QC.arbitrary
+  arbitrary = Number <$> positiveArb <*> QC.arbitrary
 
 instance QC.Arbitrary Net where
   arbitrary = pure Wire
@@ -321,10 +325,10 @@ instance QC.Arbitrary PortType where
   arbitrary = QC.oneof [PortNet <$> QC.arbitrary, Reg <$> QC.arbitrary]
 
 instance QC.Arbitrary Port where
-  arbitrary = Port <$> QC.arbitrary <*> QC.arbitrary
+  arbitrary = Port <$> QC.arbitrary <*> positiveArb <*> QC.arbitrary
 
 instance QC.Arbitrary Delay where
-  arbitrary = Delay <$> QC.suchThat QC.arbitrary (\x -> x > 0)
+  arbitrary = Delay <$> positiveArb
 
 instance QC.Arbitrary Event where
   arbitrary = EId <$> QC.arbitrary
@@ -333,7 +337,7 @@ instance QC.Arbitrary ModConn where
   arbitrary = ModConn <$> QC.arbitrary
 
 instance QC.Arbitrary ConstExpr where
-  arbitrary = ConstExpr <$> QC.suchThat QC.arbitrary (\x -> x > 0)
+  arbitrary = ConstExpr <$> positiveArb
 
 instance QC.Arbitrary RegLVal where
   arbitrary = QC.oneof [ RegId <$> QC.arbitrary
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index d4a7c9c..4410532 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : Test.VeriFuzz.VeriFuzz.Helpers
+Module      : Test.VeriFuzz.Verilog.Helpers
 Description : Defaults and common functions.
 Copyright   : (c) 2018-2019, Yann Herklotz Grave
 License     : BSD-3
@@ -10,18 +10,18 @@ Portability : POSIX
 Defaults and common functions.
 -}
 
-module Test.VeriFuzz.VeriFuzz.Helpers where
+module Test.VeriFuzz.Verilog.Helpers where
 
 import           Control.Lens
 import           Data.Text                 (Text)
 import qualified Data.Text
 import           Test.VeriFuzz.Verilog.AST
 
-regDecl :: Text -> ModItem
-regDecl = Decl . Port (Reg False) . Identifier
+regDecl :: Identifier -> ModItem
+regDecl = Decl . Port (Reg False) 1
 
-wireDecl :: Text -> ModItem
-wireDecl = Decl . Port (PortNet Wire) . Identifier
+wireDecl :: Identifier -> ModItem
+wireDecl = Decl . Port (PortNet Wire) 1
 
 modConn :: Text -> ModConn
 modConn = ModConn . PrimExpr . PrimId . Identifier
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index 6731b65..6993fef 100644
--- a/src/Test/VeriFuzz/Verilog/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -82,3 +82,8 @@ nestUpTo i src =
 instantiateMod :: ModDecl -> ModDecl -> ModDecl
 instantiateMod mod main =
   main
+
+-- | Initialise all the inputs and outputs to a module.
+initMod :: ModDecl -> ModDecl
+initMod mod =
+  mod
-- 
cgit