From 31325e890e8a7807ec5a3d996c3789baad0e8dc4 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 3 Apr 2019 19:53:56 +0100 Subject: Generate Verilog instead of ModDecl --- app/Main.hs | 2 +- src/VeriFuzz.hs | 4 ++-- stack.yaml | 1 - 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/app/Main.hs b/app/Main.hs index 4d2f0c4..19a1c7f 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -192,7 +192,7 @@ handleOpts (Fuzz _) = do num <- getNumCapabilities vars <- sequence - $ (\x -> myForkIO $ V.runEquivalence (V.randomMod 10 100) + $ (\x -> myForkIO $ V.runEquivalence (V.procedural V.defaultConfig) ("test_" <> T.pack (show x)) 0 ) diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index e008d62..b6b134b 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -113,10 +113,10 @@ checkEquivalence src dir = shellyFailDir $ do -- | Run a fuzz run and check if all of the simulators passed by checking if the -- generated Verilog files are equivalent. -runEquivalence :: Gen ModDecl -> Text -> Int -> IO () +runEquivalence :: Gen Verilog -> Text -> Int -> IO () runEquivalence gm t i = do m <- Hog.sample gm - let srcInfo = makeSrcInfo m + let srcInfo = SourceInfo "top" m rand <- generateByteString 20 shellyFailDir $ do mkdir_p (fromText "output" fromText n) diff --git a/stack.yaml b/stack.yaml index 3a00eae..128cb80 100644 --- a/stack.yaml +++ b/stack.yaml @@ -3,7 +3,6 @@ packages: - . extra-deps: - DRBG-0.5.5@sha256:3b8040bed356e2b63927a27fb6d5adbd19d70c9e1d1bb66111bbeb33e56900eb - - QuickCheck-2.9.2@sha256:93cebf9f9c55e8a941bd3166272680d67b80d9b5d95bd836765e3d4a4ef278d0 - fgl-visualize-0.1.0.1@sha256:e682066053a6e75478a08fd6822dd0143a3b8ea23244bdb01dd389a266447c5e - tasty-hedgehog-0.2.0.0@sha256:83a8b777fa472040979e44dba43c32441f55d5ddb9641a4d53deee4b0e09fa34 resolver: lts-13.14 -- cgit