From 3786929d0025b32852fd2eaa1eb281ed60a1d84b Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 3 Apr 2019 19:54:08 +0100
Subject: Fix infinite loop in state based generation

---
 src/VeriFuzz/Config.hs      |  2 +-
 src/VeriFuzz/Verilog/Gen.hs | 29 +++++++++++++++++------------
 2 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs
index b8a1062..d812248 100644
--- a/src/VeriFuzz/Config.hs
+++ b/src/VeriFuzz/Config.hs
@@ -75,7 +75,7 @@ defaultValue
 defaultValue x = Toml.dimap Just (fromMaybe x) . Toml.dioptional
 
 defaultConfig :: Config
-defaultConfig = Config (Probability 10 1 5 1 1) (Property 50 Nothing 3)
+defaultConfig = Config (Probability 5 1 5 1 1) (Property 20 Nothing 3)
 
 twoKey :: Toml.Piece -> Toml.Piece -> Toml.Key
 twoKey a b = Toml.Key (a :| [b])
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 3d508c6..092f5f0 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -160,27 +160,32 @@ statement = do
         ]
     where onDepth c n = if c ^. stmntDepth > 0 then n else 0
 
+always :: StateGen ModItem
+always = do
+    stat     <- SeqBlock <$> some statement
+    eventReg <- select Reg
+    return $ Always (EventCtrl (EId (eventReg ^. portName)) (Just stat))
+
 -- | Generate a random module item.
 modItem :: StateGen ModItem
 modItem = do
-    prob     <- askProbability
-    stat     <- fold <$> some statement
-    eventReg <- select Reg
-    modCA    <- ModCA <$> contAssign
-    gen $ Hog.frequency
-        [ (prob ^. probAssign, return modCA)
-        , ( prob ^. probAlways
-          , return $ Always (EventCtrl (EId (eventReg ^. portName)) (Just stat))
-          )
+    prob <- askProbability
+    Hog.frequency
+        [ (prob ^. probAssign, ModCA <$> contAssign)
+        , (prob ^. probAlways, always)
         ]
 
+moduleName :: Maybe Identifier -> StateGen Identifier
+moduleName (Just t) = return t
+moduleName Nothing  = gen arb
+
 -- | Generates a module definition randomly. It always has one output port which
 -- is set to @y@. The size of @y@ is the total combination of all the locally
 -- defined wires, so that it correctly reflects the internal state of the
 -- module.
-moduleDef :: Bool -> StateGen ModDecl
+moduleDef :: Maybe Identifier -> StateGen ModDecl
 moduleDef top = do
-    name     <- if top then return "top" else gen arb
+    name     <- moduleName top
     portList <- some $ newPort Wire
     mi       <- some modItem
     context  <- get
@@ -196,7 +201,7 @@ moduleDef top = do
 procedural :: Config -> Gen Verilog
 procedural config = Verilog . (: []) . Description <$> Hog.resize
     num
-    (runReaderT (evalStateT (moduleDef True) context) config)
+    (runReaderT (evalStateT (moduleDef (Just "top")) context) config)
   where
     context = Context [] 0 $ config ^. configProperty . propDepth
     num     = fromIntegral $ config ^. configProperty . propSize
-- 
cgit