From 3eb5b42c118c555aea736b5ca9b685ecdf72bd14 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 3 Apr 2019 17:30:43 +0100
Subject: Add Vivado module

---
 src/VeriFuzz/Sim/Template.hs | 12 +++++++++++
 src/VeriFuzz/Sim/Vivado.hs   | 48 ++++++++++++++++++++++++++++++++++++++++++++
 verifuzz.cabal               |  1 +
 3 files changed, 61 insertions(+)
 create mode 100644 src/VeriFuzz/Sim/Vivado.hs

diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs
index 5226106..bd58b83 100644
--- a/src/VeriFuzz/Sim/Template.hs
+++ b/src/VeriFuzz/Sim/Template.hs
@@ -16,6 +16,7 @@ module VeriFuzz.Sim.Template
     ( yosysSatConfig
     , yosysSimConfig
     , xstSynthConfig
+    , vivadoSynthConfig
     , sbyConfig
     )
 where
@@ -73,6 +74,17 @@ xstSynthConfig top = [st|run
 -change_error_to_warning "HDLCompiler:226 HDLCompiler:1832"
 |]
 
+-- brittany-disable-next-binding
+vivadoSynthConfig :: Text -> Text -> Text
+vivadoSynthConfig top outf = [st|
+# CRITICAL WARNING: [Synth 8-5821] Potential divide by zero
+set_msg_config -id {Synth 8-5821} -new_severity {WARNING}
+
+read_verilog rtl.v
+synth_design -part xc7k70t -top #{top}
+write_verilog -force #{outf}
+|]
+
 -- brittany-disable-next-binding
 sbyConfig :: (Tool a, Tool b) => FilePath -> a -> Maybe b -> SourceInfo -> Text
 sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options]
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
new file mode 100644
index 0000000..fef0c83
--- /dev/null
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -0,0 +1,48 @@
+{-|
+Module      : VeriFuzz.Sim.Vivado
+Description : Vivado Synthesisor implementation.
+Copyright   : (c) 2019, Yann Herklotz Grave
+License     : GPL-3
+Maintainer  : ymherklotz [at] gmail [dot] com
+Stability   : experimental
+Portability : POSIX
+
+Vivado Synthesisor implementation.
+-}
+
+module VeriFuzz.Sim.Vivado
+    ( Vivado(..)
+    , defaultVivado
+    )
+where
+
+import           Prelude                  hiding (FilePath)
+import           Shelly
+import           VeriFuzz.Sim.Internal
+import           VeriFuzz.Sim.Template
+import           VeriFuzz.Verilog.CodeGen
+
+newtype Vivado = Vivado { vivadoPath :: FilePath }
+               deriving (Eq, Show)
+
+instance Tool Vivado where
+    toText _ = "vivado"
+
+instance Synthesisor Vivado where
+    runSynth = runSynthVivado
+
+defaultVivado :: Vivado
+defaultVivado = Vivado "vivado"
+
+runSynthVivado :: Vivado -> SourceInfo -> FilePath -> Sh ()
+runSynthVivado sim (SourceInfo top src) outf = do
+    dir <- pwd
+    writefile vivadoTcl . vivadoSynthConfig top $ toTextIgnore outf
+    writefile "rtl.v" $ genSource src
+    echoP "Vivado: run"
+    logger_ dir "vivado"
+        $ timeout
+              (vivadoPath sim)
+              ["-mode", "batch", "-source", toTextIgnore vivadoTcl]
+    echoP "Vivado: done"
+    where vivadoTcl = "vivado_" <> fromText top <.> "tcl"
diff --git a/verifuzz.cabal b/verifuzz.cabal
index 7830465..5ed7497 100644
--- a/verifuzz.cabal
+++ b/verifuzz.cabal
@@ -41,6 +41,7 @@ library
                  , VeriFuzz.Sim.Internal
                  , VeriFuzz.Sim.Reduce
                  , VeriFuzz.Sim.Template
+                 , VeriFuzz.Sim.Vivado
                  , VeriFuzz.Sim.XST
                  , VeriFuzz.Sim.Yosys
                  , VeriFuzz.Verilog
-- 
cgit