From 425fbf1f675cfd47265999cc522bf1121a43efb1 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Sun, 24 Nov 2019 18:00:01 +0000
Subject: Add ModConnNamed in testbench

---
 src/Verismith/Verilog/Mutate.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Verismith/Verilog/Mutate.hs b/src/Verismith/Verilog/Mutate.hs
index 586e085..a4a188b 100644
--- a/src/Verismith/Verilog/Mutate.hs
+++ b/src/Verismith/Verilog/Mutate.hs
@@ -244,7 +244,7 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
             ^.. modItems
             .   traverse
             .   modInstId
-    conns = ModConn . Id <$> allVars m
+    conns = uncurry ModConnNamed . fmap Id <$> zip (allVars m) (allVars m)
 
 -- | Instantiate without adding wire declarations. It also does not count the
 -- current instantiations of the same module.
-- 
cgit