From 7d68a1e7ec557e62615a7f9eea438cff7805b120 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 9 Nov 2018 21:43:19 +0000 Subject: Add testbench to the end --- src/Test/VeriFuzz/CodeGen.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Test/VeriFuzz/CodeGen.hs b/src/Test/VeriFuzz/CodeGen.hs index 6cf2d27..80f813e 100644 --- a/src/Test/VeriFuzz/CodeGen.hs +++ b/src/Test/VeriFuzz/CodeGen.hs @@ -22,7 +22,7 @@ generate graph = <> ");\n" <> fromList (imap " input wire " ";\n" inp) <> fromList (imap " output wire " ";\n" out) - <> "endmodule\n" + <> "endmodule\n\nmodule main;\n initial\n begin\n $display(\"Hello, world\");\n $finish;\n end\nendmodule" where and a b c = a == b && a /= c inputs n = indeg graph n == 0 && outdeg graph n /= 0 -- cgit