From 83ad6d594a76d9b9b55e8027df94ad7ae22b0ff3 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 29 Dec 2018 19:40:24 +0100 Subject: Add more info to README --- README.md | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 4b15707..12e48e4 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,10 @@ -![Build Status](https://travis-ci.com/ymherklotz/verifuzz.svg?token=qfBKKGwxeWkjDsy7e16x&branch=master) +# VeriFuzz ![Build Status](https://travis-ci.com/ymherklotz/verifuzz.svg?token=qfBKKGwxeWkjDsy7e16x&branch=master) -# verifuzz +Verilog Fuzzer to test the major verilog compilers by generating random, valid +verilog. -Verilog Fuzzer to test the major verilog compilers by generating random, valid verilog. +It currently supports the following simulators: + +- [Yosys](http://www.clifford.at/yosys/) +- [Icarus Verilog](http://iverilog.icarus.com) +- [Xst](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm) -- cgit