From 856e4fb7ec3e7ba59c6d9fceed215dde832441f5 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 13 Nov 2019 18:36:29 +0000 Subject: Add icarus verilog bug --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README.md b/README.md index 96f7d62..c0b18c6 100644 --- a/README.md +++ b/README.md @@ -50,6 +50,12 @@ The fuzzer generates combinational and behavioural Verilog to test the various t | Mis-synthesis | [Forum 982518](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Signed-with-shift-in-condition-synthesis-mistmatch/td-p/982518) | ✓ | 𐄂 | | Mis-synthesis | [Forum 982419](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Bit-selection-synthesis-mismatch/td-p/982419) | ✓ | 𐄂 | +### Icarus Verilog + +| Type | Issue | Confirmed | Fixed | +|----------------|-----------------------------------------------------------------|-----------|-------| +| Mis-simulation | [Issue 283](https://github.com/steveicarus/iverilog/issues/283) | ✓ | 𐄂 | + ## Install the Fuzzer The fuzzer now supports building with [nix](https://nixos.org/nix/manual/), which pulls in all the extra dependencies that are needed to build the project. The main files and their functions are described below: -- cgit