From 9b3405316b630fc96d6c4980c7f227c1fd005e6e Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 1 Dec 2018 15:11:52 +0000
Subject: Fix data types and apply more hlint suggestions

---
 src/Test/VeriFuzz/VerilogAST.hs | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs
index 53efad1..109f024 100644
--- a/src/Test/VeriFuzz/VerilogAST.hs
+++ b/src/Test/VeriFuzz/VerilogAST.hs
@@ -63,14 +63,14 @@ data Port = Port { _portName :: Identifier
                  } deriving (Show)
 makeLenses ''Port
 
-data ModuleItem = Assign ContAssign
+newtype ModuleItem = Assign ContAssign
                    deriving (Show)
 makeLenses ''ModuleItem
 
 -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
-data ModuleDecl = ModuleDecl { _moduleId   :: Identifier
-                             , _modPorts   :: [Port]
-                             , _moduleItem :: ModuleItem
+data ModuleDecl = ModuleDecl { _moduleId    :: Identifier
+                             , _modPorts    :: [Port]
+                             , _moduleItems :: [ModuleItem]
                              } deriving (Show)
 makeLenses ''ModuleDecl
 
@@ -86,9 +86,7 @@ numExpr :: Int -> Int -> Expression
 numExpr = ((PrimExpr . PrimNum) .) . Number
 
 emptyMod :: ModuleDecl
-emptyMod =
-  ModuleDecl (Identifier "") [] $ Assign $ ContAssign (Identifier "") $
-  OpExpr (numExpr 32 0) BinAnd (numExpr 32 0)
+emptyMod = ModuleDecl (Identifier "") [] []
 
 setModName :: Text -> ModuleDecl -> ModuleDecl
-setModName str = moduleId .~ (Identifier str)
+setModName str = moduleId .~ Identifier str
-- 
cgit