From a59af9347e35cb5b7909d05e0d9318e974515497 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 1 Aug 2019 01:38:47 +0200 Subject: Fix to read the verilog instead of a formal repr --- src/VeriFuzz/Sim/Yosys.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index d69bc69..8c73b86 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -73,7 +73,7 @@ runSynthYosys sim (SourceInfo _ src) = do "yosys" (yosysPath sim) [ "-p" - , "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out + , "read_verilog " <> inp <> "; synth; write_verilog -noattr " <> out ] where inpf = "rtl.v" -- cgit