From c6ee6729e637590627779ddc5c1a46b865eb6bd4 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 3 Dec 2019 17:48:47 +0000 Subject: More minimisation --- README.md | 2 ++ src/Verismith/Fuzz.hs | 12 +++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 5726414..638c94c 100644 --- a/README.md +++ b/README.md @@ -42,6 +42,8 @@ The fuzzer generates combinational and behavioural Verilog to test the various t ### Vivado + + | Type | Issue | Confirmed | Fixed | |---------------|-------------------------------------------------------------------------------------------------------------------------------------|-----------|-------| | Crash | [Forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) | ✓ | ✗ | diff --git a/src/Verismith/Fuzz.hs b/src/Verismith/Fuzz.hs index 2db0b7b..f111118 100644 --- a/src/Verismith/Fuzz.hs +++ b/src/Verismith/Fuzz.hs @@ -382,9 +382,15 @@ reduction src = do _ <- liftSh $ mapM (redSim datadir) simFails return () where - red datadir (SynthResult a b _ _) = reduceSynth datadir a b src - redSynth a = reduceSynthesis a src - redSim datadir (SimResult t _ bs _ _) = reduceSimIc datadir bs t src + red datadir (SynthResult a b _ _) = do + r <- reduceSynth datadir a b src + writefile (fromText $ "reduce_" <> toText a <> "_" <> toText b <> ".v") $ genSource r + redSynth a = do + r <- reduceSynthesis a src + writefile (fromText $ "reduce_" <> toText a <> ".v") $ genSource r + redSim datadir (SimResult t _ bs _ _) = do + r <- reduceSimIc datadir bs t src + writefile (fromText $ "reduce_sim_" <> toText t <> ".v") $ genSource r titleRun :: (MonadIO m, MonadSh m) => Text -> Fuzz m a -> Fuzz m (NominalDiffTime, a) -- cgit