From d1b04fc068b1484f8bd0020598d3a2f023772f46 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 11 May 2020 22:28:35 +0100 Subject: Tests passing for new reduction --- src/Verismith/Reduce.hs | 4 ++++ src/Verismith/Verilog/Mutate.hs | 10 +++++++++- test/Parser.hs | 2 +- test/Reduce.hs | 39 +++++++++++++++++++++++---------------- 4 files changed, 37 insertions(+), 18 deletions(-) diff --git a/src/Verismith/Reduce.hs b/src/Verismith/Reduce.hs index 8595066..6b18232 100644 --- a/src/Verismith/Reduce.hs +++ b/src/Verismith/Reduce.hs @@ -35,6 +35,9 @@ module Verismith.Reduce , removeConstInConcat , takeReplace , filterExpr + , ReduceAnn(..) + , tagAlways + , untagAlways ) where @@ -61,6 +64,7 @@ import Verismith.Verilog import Verismith.Verilog.AST import Verismith.Verilog.Mutate import Verismith.Verilog.Parser +import Verismith.Verilog.CodeGen -- $strategy diff --git a/src/Verismith/Verilog/Mutate.hs b/src/Verismith/Verilog/Mutate.hs index 260d759..b48ab11 100644 --- a/src/Verismith/Verilog/Mutate.hs +++ b/src/Verismith/Verilog/Mutate.hs @@ -106,6 +106,9 @@ instance Mutate Assign where instance Mutate ContAssign where mutExpr f (ContAssign a e) = ContAssign a $ f e +instance Mutate (CasePair ann) where + mutExpr f (CasePair e s) = CasePair (f e) $ mutExpr f s + instance Mutate (Statement ann) where mutExpr f (TimeCtrl d s) = TimeCtrl d $ mutExpr f <$> s mutExpr f (EventCtrl e s) = EventCtrl e $ mutExpr f <$> s @@ -116,6 +119,8 @@ instance Mutate (Statement ann) where mutExpr f (SysTaskEnable a) = SysTaskEnable $ mutExpr f a mutExpr f (CondStmnt a b c) = CondStmnt (f a) (mutExpr f <$> b) $ mutExpr f <$> c mutExpr f (ForLoop a1 e a2 s) = ForLoop a1 e a2 $ mutExpr f s + mutExpr f (StmntAnn a s) = StmntAnn a $ mutExpr f s + mutExpr f (StmntCase t e cp cd) = StmntCase t (f e) (mutExpr f cp) $ mutExpr f cd instance Mutate Parameter where mutExpr _ = id @@ -128,12 +133,15 @@ instance Mutate (ModItem ann) where mutExpr f (ModInst a b conns) = ModInst a b $ mutExpr f conns mutExpr f (Initial s) = Initial $ mutExpr f s mutExpr f (Always s) = Always $ mutExpr f s + mutExpr f (ModItemAnn a s) = ModItemAnn a $ mutExpr f s mutExpr _ d@Decl{} = d mutExpr _ p@ParamDecl{} = p mutExpr _ l@LocalParamDecl{} = l instance Mutate (ModDecl ann) where - mutExpr f (ModDecl a b c d e) = ModDecl (mutExpr f a) (mutExpr f b) (mutExpr f c) (mutExpr f d) (mutExpr f e) + mutExpr f (ModDecl a b c d e) = + ModDecl (mutExpr f a) (mutExpr f b) (mutExpr f c) (mutExpr f d) (mutExpr f e) + mutExpr f (ModDeclAnn a m) = ModDeclAnn a $ mutExpr f m instance Mutate (Verilog ann) where mutExpr f (Verilog a) = Verilog $ mutExpr f a diff --git a/test/Parser.hs b/test/Parser.hs index 5ae9d4c..0ce5817 100644 --- a/test/Parser.hs +++ b/test/Parser.hs @@ -58,7 +58,7 @@ parserIdempotentMod = Hog.property $ do parserInput :: Property parserInput = Hog.property $ do - v <- Hog.forAll (GenVerilog <$> procedural "top" smallConfig) + v <- Hog.forAll (GenVerilog <$> (procedural "top" smallConfig :: Gen (Verilog ()))) Hog.assert . isRight $ parse parseModDecl "input_test" (alexScanTokens . uncomment "test" $ show v) diff --git a/test/Reduce.hs b/test/Reduce.hs index afd5e0a..47554bf 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -24,7 +24,7 @@ import Verismith import Verismith.Reduce import Data.Text (Text) -sourceInfo :: Text -> Verilog () -> SourceInfo () +sourceInfo :: Text -> Verilog ReduceAnn -> SourceInfo ReduceAnn sourceInfo = SourceInfo reduceUnitTests :: TestTree @@ -303,7 +303,7 @@ endmodule halveStatementsTest :: TestTree halveStatementsTest = testCase "Statements" $ do - GenVerilog <$> halveStatements "top" srcInfo1 @?= golden1 + GenVerilog <$> halveStatements "top" (tagAlways "top" srcInfo1) @?= golden1 where srcInfo1 = sourceInfo "top" [verilog| module top(clk, y, x); @@ -327,7 +327,7 @@ module top(clk, y, x); assign y = {r1, r2, r3}; endmodule |] - golden1 = GenVerilog <$> Dual (sourceInfo "top" [verilog| + golden1 = GenVerilog <$> Dual (tagAlways "top" $ sourceInfo "top" [verilog| module top(clk, y, x); input clk; input x; @@ -336,15 +336,17 @@ module top(clk, y, x); reg r2; reg r3; always @(posedge clk) begin - r1 <= 1'b0; + r1 <= r3; end always @(posedge clk) begin - r1 <= 1'b0; + r1 <= r2; + r2 <= r3; + r3 <= r1; end - assign y = {r1, 1'b0, 1'b0}; + assign y = {r1, r2, r3}; endmodule -|]) (sourceInfo "top" [verilog| +|]) (tagAlways "top" $ sourceInfo "top" [verilog| module top(clk, y, x); input clk; input x; @@ -353,15 +355,16 @@ module top(clk, y, x); reg r2; reg r3; always @(posedge clk) begin - r2 <= 1'b0; + r2 <= r1; r3 <= r2; end always @(posedge clk) begin + r1 <= r2; r2 <= r3; - r3 <= 1'b0; + r3 <= r1; end - assign y = {1'b0, r2, r3}; + assign y = {r1, r2, r3}; endmodule |]) @@ -405,7 +408,7 @@ statementReducerTest = testCase "Statement reducer" $ do GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1 GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2 where - srcInfo1 = sourceInfo "top" [verilog| + srcInfo1 = tagAlways "top" $ sourceInfo "top" [verilog| module top(y, x); output wire [4:0] y; input wire [4:0] x; @@ -425,7 +428,7 @@ module top(y, x); end endmodule |] - golden1 = Dual (sourceInfo "top" [verilog| + golden1 = Dual (tagAlways "top" $ sourceInfo "top" [verilog| module top(y, x); output wire [4:0] y; input wire [4:0] x; @@ -438,9 +441,11 @@ module top(y, x); always @(posedge clk) begin a <= 1; b <= 2; + c <= 3; + d <= 4; end endmodule -|]) $ sourceInfo "top" [verilog| +|]) . tagAlways "top" $ sourceInfo "top" [verilog| module top(y, x); output wire [4:0] y; input wire [4:0] x; @@ -451,12 +456,14 @@ module top(y, x); end always @(posedge clk) begin + a <= 1; + b <= 2; c <= 3; d <= 4; end endmodule |] - srcInfo2 = sourceInfo "top" [verilog| + srcInfo2 = tagAlways "top" $ sourceInfo "top" [verilog| module top(y, x); output wire [4:0] y; input wire [4:0] x; @@ -469,7 +476,7 @@ module top(y, x); end endmodule |] - golden2 = Dual (sourceInfo "top" [verilog| + golden2 = Dual (tagAlways "top" $ sourceInfo "top" [verilog| module top(y, x); output wire [4:0] y; input wire [4:0] x; @@ -477,7 +484,7 @@ module top(y, x); always @(posedge clk) y <= 2; endmodule -|]) $ sourceInfo "top" [verilog| +|]) . tagAlways "top" $ sourceInfo "top" [verilog| module top(y, x); output wire [4:0] y; input wire [4:0] x; -- cgit