From e4b2455be384c95a9ab87881db01841a13bfec88 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 14 Nov 2019 17:21:22 +0000
Subject: Update description

---
 bugs/yosys_11.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bugs/yosys_11.md b/bugs/yosys_11.md
index 3247135..341155c 100644
--- a/bugs/yosys_11.md
+++ b/bugs/yosys_11.md
@@ -23,7 +23,7 @@ module top(y, clk);
 endmodule
 ```
 
-However, in Yosys 0.9 it is compiled to:
+However, in Yosys 0.9 it is compiled to the following, which outputs a constant one after the first clock cycle:
 
 ```verilog
 /* Generated by Yosys 0.9 (git sha1 1979e0b1, clang 7.0.1-8 -fPIC -Os) */
-- 
cgit