From e5a7cfbaeaac6a5f9ca9a7cd9883cf788417681a Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Fri, 9 Nov 2018 21:37:29 +0000
Subject: Generate some Verilog code from graph

---
 src/Main.hs                  | 15 ++++++---------
 src/Test/VeriFuzz/CodeGen.hs | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/src/Main.hs b/src/Main.hs
index 5eebc30..513b8cc 100644
--- a/src/Main.hs
+++ b/src/Main.hs
@@ -1,24 +1,21 @@
 module Main where
 
-import Data.Bits
-import Test.QuickCheck hiding ((.&.))
 import Data.GraphViz
-import Data.Graph.Inductive.Example (clr479, dag4)
-import Data.Graph.Inductive.Graph
+import Data.Graph.Inductive
 import Data.Graph.Inductive.PatriciaTree
 import Data.GraphViz.Attributes.Complete
-import Data.Text.Lazy
 import Data.GraphViz.Commands
-import System.Random.MWC
+import Data.Text.Lazy
+import Data.Text.IO as T
 
-import Test.VeriFuzz.Graph.Random
-import Test.VeriFuzz.Types
+import Test.VeriFuzz
 
 instance Labellable Gate where
   toLabelValue gate = StrLabel . pack $ show gate
 
-main :: IO FilePath
+main :: IO ()
 --main = sample (arbitrary :: Gen (Circuit Input))
 main = do
   gr <- (randomDAG 100 :: IO (Gr Gate ()))
   runGraphviz (graphToDot quickParams $ emap (\_ -> "") gr) Png "output.png"
+  T.putStrLn $ generate gr
diff --git a/src/Test/VeriFuzz/CodeGen.hs b/src/Test/VeriFuzz/CodeGen.hs
index 3965b16..6cf2d27 100644
--- a/src/Test/VeriFuzz/CodeGen.hs
+++ b/src/Test/VeriFuzz/CodeGen.hs
@@ -1 +1,33 @@
+{-# LANGUAGE OverloadedStrings #-}
+
 module Test.VeriFuzz.CodeGen where
+
+import Data.Text (Text, empty, pack)
+import Data.Graph.Inductive (Graph, Node, indeg, outdeg, nodes)
+
+import Test.VeriFuzz.Types
+
+fromNode :: Node -> Text
+fromNode node = pack $ "w" <> show node
+
+filterGr :: (Graph gr) => gr n e -> (Node -> Bool) -> [Node]
+filterGr graph f =
+  filter f $ nodes graph
+
+generate :: (Graph gr) => gr Gate e -> Text
+generate graph =
+  "module generated_module(\n"
+  <> fromList (imap "  " ",\n" inp)
+  <> fromList (imap "  " ",\n" out)
+  <> ");\n"
+  <> fromList (imap "  input wire " ";\n" inp)
+  <> fromList (imap "  output wire " ";\n" out)
+  <> "endmodule\n"
+  where
+    and a b c = a == b && a /= c
+    inputs n = indeg graph n == 0 && outdeg graph n /= 0
+    outputs n = indeg graph n /= 0 && outdeg graph n == 0
+    fromList = foldl mappend empty
+    inp = filterGr graph inputs
+    out = filterGr graph outputs
+    imap b e = map ((\s -> b <> s <> e) . fromNode)
-- 
cgit