From edc2b13ecc3c6e8aebf61d3569cd50ddd807fbc2 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 12 May 2020 21:19:23 +0100
Subject: Add for loops and events to reduction

---
 src/Verismith/Reduce.hs | 19 ++++++++++++++++++-
 test/Reduce.hs          | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/src/Verismith/Reduce.hs b/src/Verismith/Reduce.hs
index dde2c8b..6df398d 100644
--- a/src/Verismith/Reduce.hs
+++ b/src/Verismith/Reduce.hs
@@ -249,6 +249,7 @@ relevantModItem _ _ = False
 isAssign :: (Statement ReduceAnn) -> Bool
 isAssign (BlockAssign _) = True
 isAssign (NonBlockAssign _) = True
+isAssign (ForLoop _ _ _ _) = True
 isAssign _ = False
 
 lValName :: LVal -> [Identifier]
@@ -320,6 +321,18 @@ fixModInst (SourceInfo _ (Verilog decl)) (ModInst n g i) = case m of
       | otherwise = Nothing
 fixModInst _ a = a
 
+eventIdent :: Event -> [Identifier]
+eventIdent (EId i) = [i]
+eventIdent (EExpr e) =
+  case exprId e of
+    Nothing -> []
+    Just eid -> [eid]
+eventIdent EAll = []
+eventIdent (EPosEdge i) = [i]
+eventIdent (ENegEdge i) = [i]
+eventIdent (EOr e1 e2) = eventIdent e1 <> eventIdent e2
+eventIdent (EComb e1 e2) = eventIdent e1 <> eventIdent e2
+
 findActiveWires :: Identifier -> (SourceInfo ReduceAnn) -> [Identifier]
 findActiveWires t src =
   nub $
@@ -329,12 +342,16 @@ findActiveWires t src =
       <> fmap portToId o
       <> fmap paramToId p
       <> modinstwires
+      <> events
   where
     assignWires = m ^.. modItems . traverse . modContAssign . contAssignNetLVal
     assignStat =
       concatMap lValName $
         (allStat ^.. traverse . stmntBA . assignReg)
           <> (allStat ^.. traverse . stmntNBA . assignReg)
+          <> (allStat ^.. traverse . forAssign . assignReg)
+          <> (allStat ^.. traverse . forIncr . assignReg)
+    events = concatMap eventIdent $ (allStat ^.. traverse . statEvent)
     allStat = filter isAssign . concat $ fmap universe stat
     stat =
       (m ^.. modItems . traverse . _Initial)
@@ -405,7 +422,7 @@ halveModules srcInfo@(SourceInfo top _) =
     . addMod main
     <$> combine (infoSrc . _Wrapped) repl srcInfo
   where
-    repl = remove1 . filter (not . matchesModName (Identifier top))
+    repl = halve . filter (not . matchesModName (Identifier top))
     main = srcInfo ^. mainModule
 
 moduleBot :: (SourceInfo ReduceAnn) -> Bool
diff --git a/test/Reduce.hs b/test/Reduce.hs
index e6cc8ff..85a0654 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -261,6 +261,7 @@ activeWireTest = testCase "Active wires" $ do
   findActiveWires "top" verilog2 \\ ["x", "y", "z"] @?= []
   findActiveWires "top" verilog3 \\ ["x", "y", "clk", "r1", "r2"] @?= []
   findActiveWires "top" verilog4 \\ ["x", "y", "w", "a", "b"] @?= []
+  findActiveWires "top" verilog5 \\ ["r2", "r1", "x", "y"] @?= []
   where
     verilog1 =
       sourceInfo
@@ -338,6 +339,23 @@ module m2(y, z, x);
   output y;
   output z;
 endmodule
+|]
+    verilog5 =
+      sourceInfo
+        "top"
+        [verilog|
+module top(y, x);
+  input x;
+  output y;
+  reg r1;
+  reg r2;
+  reg r3;
+  always @* begin
+    for (r1 = 1; r1 < 2; r1 = r1 + 1) begin
+      r2 <= 1'b0;
+    end
+  end
+endmodule
 |]
 
 halveStatementsTest :: TestTree
-- 
cgit