From f3268d934a9a2b01633b5f7a3353d1a97c40a9df Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 5 Jun 2019 13:26:47 +0100 Subject: Fix size in output wire --- src/VeriFuzz/Verilog/Gen.hs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index cb3a8ad..c8860ce 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -464,9 +464,10 @@ moduleDef top = do $ local ^.. traverse . portSize + let combine = config ^. configProperty . propCombine let clock = Port Wire False 1 "clk" - let yport = if True then Port Wire False 1 "y" else Port Wire False size "y" - let comb = combineAssigns_ (config ^. configProperty . propCombine) yport local + let yport = if combine then Port Wire False 1 "y" else Port Wire False size "y" + let comb = combineAssigns_ combine yport local return . declareMod local . ModDecl name [yport] (clock : portList) (comb : mi) -- cgit