From f4dbd5a813de78a9241573a498a9bb1cb40c65f3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Sun, 2 Jun 2019 13:25:37 +0100
Subject: Remove dead code

---
 src/VeriFuzz/Verilog/Gen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 828224f..c903e28 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -464,7 +464,7 @@ moduleDef top = do
                 ^.. traverse
                 .   portSize
     let clock = Port Wire False 1 "clk"
-    let yport = Port Wire False 1 "y"
+    let yport = if True then Port Wire False 1 "y" else Port Wire False size "y"
     let comb  = combineAssigns_ yport local
     return
         . declareMod local
-- 
cgit