From f6825b9ba251837a649e8ef4d2446e4876696b65 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 24 Nov 2019 13:02:38 +0000 Subject: Fix counter-example simulation run --- src/Verismith/Fuzz.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Verismith/Fuzz.hs b/src/Verismith/Fuzz.hs index c38601a..c73f8e4 100644 --- a/src/Verismith/Fuzz.hs +++ b/src/Verismith/Fuzz.hs @@ -324,7 +324,7 @@ simulation src = do pop dir $ do liftSh $ do cp (fromText ".." fromText (toText a) synthOutput a) $ synthOutput a - writefile "rtl.v" $ genSource src + writefile "syn_identity.v" $ genSource src ident <- runSimIcEC datadir defaultIcarus defaultIdentitySynth src b Nothing runSimIcEC datadir defaultIcarus a src b (Just ident) where dir = fromText $ "countereg_sim_" <> toText a -- cgit