From f7bffa59bfd1eb4bece108ce63459670ac1c183b Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 23 Jul 2021 12:56:07 +0200
Subject: Add paranthesis

---
 src/Verismith/Verilog/CodeGen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Verismith/Verilog/CodeGen.hs b/src/Verismith/Verilog/CodeGen.hs
index 7f5dd46..62102c3 100644
--- a/src/Verismith/Verilog/CodeGen.hs
+++ b/src/Verismith/Verilog/CodeGen.hs
@@ -60,7 +60,7 @@ moduleDecl (ModDecl i outP inP items ps) =
     modI = vsep $ moduleItem <$> items
     outIn = outP ++ inP
     params [] = ""
-    params (p : pps) = hcat ["#", paramList (p :| pps)]
+    params (p : pps) = hcat ["#(", paramList (p :| pps), ")"]
 moduleDecl (ModDeclAnn a m) = sep [hsep ["/*", pretty $ show a, "*/"], moduleDecl m]
 
 -- | Generates a parameter list. Can only be called with a 'NonEmpty' list.
-- 
cgit