From 24cf9ce5bf673615ebe36f5ab5d0ff7685dfada6 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 25 Jun 2019 22:32:21 +0100 Subject: Add back the simulation --- README.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 2d0588e..829f3b0 100644 --- a/README.md +++ b/README.md @@ -3,14 +3,17 @@ Verilog Fuzzer to test the major verilog compilers by generating random, valid verilog. -It currently supports the following simulators: +It currently supports the following synthesisers: - [Yosys](http://www.clifford.at/yosys/) -- [Icarus Verilog](http://iverilog.icarus.com) - [Xst](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm) - [Vivado](https://www.xilinx.com/products/design-tools/ise-design-suite.html) - [Quartus](https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html) +and the following simulator: + +- [Icarus Verilog](http://iverilog.icarus.com) + ## Build the Fuzzer The fuzzer is split into an executable (in the [app](/app) folder) and a -- cgit