From d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sun, 20 Jan 2019 16:49:17 +0000
Subject: Prettify files

---
 app/Main.hs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'app/Main.hs')

diff --git a/app/Main.hs b/app/Main.hs
index c13d4c2..aeda625 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -43,7 +43,10 @@ runEquivalence t = do
           ^.. getVerilogSrc
           .   traverse
           .   getDescription
-  shelly . chdir_p (fromText "equiv" </> fromText t) . verbosely $ runEquiv defaultYosys defaultYosys (Just defaultXst) circ
+  shelly . chdir_p (fromText "equiv" </> fromText t) . verbosely $ runEquiv defaultYosys
+                                                                            defaultYosys
+                                                                            (Just defaultXst)
+                                                                            circ
 
 main :: IO ()
  --main = sample (arbitrary :: Gen (Circuit Input))
-- 
cgit