From 1e4798b9bfe090ac68c2edd036637b6bfac5c06b Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 6 May 2019 18:59:08 +0100 Subject: Support multiple reg assigns in if statements --- app/Main.hs | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'app') diff --git a/app/Main.hs b/app/Main.hs index 8da1151..861fcd0 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -193,9 +193,13 @@ argparse = <> metavar "config" ) +version :: Parser (a -> a) +version = infoOption V.versionInfo $ mconcat + [long "version", short 'v', help "Show version information.", hidden] + opts :: ParserInfo Opts opts = info - (argparse <**> helper) + (argparse <**> helper <**> version) ( fullDesc <> progDesc "Fuzz different simulators and synthesisers." <> header @@ -206,7 +210,7 @@ getConfig :: Maybe FilePath -> IO V.Config getConfig = maybe (return V.defaultConfig) V.parseConfigFile handleOpts :: Opts -> IO () -handleOpts (Fuzz out configF _ _ n) = do +handleOpts (Fuzz _ configF _ _ n) = do config <- getConfig configF _ <- V.runFuzz config V.defaultYosys @@ -216,7 +220,7 @@ handleOpts (Generate f c) = do config <- getConfig c source <- V.proceduralIO "top" config maybe (T.putStrLn $ V.genSource source) - (flip T.writeFile (V.genSource source)) + (flip T.writeFile $ V.genSource source) f handleOpts (Parse f) = do verilogSrc <- readFile file -- cgit