From 51da0af5f0bc7c08e0c8824b474384a7f2752f49 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 27 Dec 2018 10:38:26 +0100 Subject: Generate completely random verilog --- app/Main.hs | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'app') diff --git a/app/Main.hs b/app/Main.hs index a7e3d7e..ab90e29 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -16,8 +16,10 @@ instance Gviz.Labellable Gate where main :: IO () --main = sample (arbitrary :: Gen (Circuit Input)) main = do - gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) + --gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) -- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png", -- T.putStrLn $ generate gr - --g <- QC.generate (QC.arbitrary :: QC.Gen SourceText) - render . genSourceText . addTestBench . nestUpTo 20 . generateAST $ Circuit gr + g <- QC.generate (QC.arbitrary :: QC.Gen SourceText) + --render . genSourceText . addTestBench . nestUpTo 20 . generateAST $ Circuit gr + + render . genSourceText . addTestBench $ g -- cgit