From bdf9a79502ffd79cdea9dc3678ee0f61b16fdea9 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Tue, 5 Feb 2019 15:21:06 +0000
Subject: Add completely random module generation

---
 app/Simulation.hs | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'app')

diff --git a/app/Simulation.hs b/app/Simulation.hs
index 675a7dc..28950c2 100644
--- a/app/Simulation.hs
+++ b/app/Simulation.hs
@@ -55,7 +55,8 @@ runSimulation = do
   let circ =
         head $ (nestUpTo 30 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription
   rand <- genRandom 20
-  val  <- shelly $ runSim defaultIcarus (initMod circ) rand
+  rand2 <- QC.generate (randomMod 10 100)
+  val  <- shelly $ runSim defaultIcarus (rand2) rand
   T.putStrLn . decodeUtf8 $ (L.toStrict . toLazyByteString . byteStringHex $ val)
 
 onFailure :: Text -> RunFailed -> Sh ()
-- 
cgit