From e827635e34079c8ee9c9e7273a59c905274e553d Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 14 Nov 2019 16:49:42 +0000 Subject: Update bug reports --- bugs/icarus_10.md | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'bugs/icarus_10.md') diff --git a/bugs/icarus_10.md b/bugs/icarus_10.md index ea9959d..57a954e 100644 --- a/bugs/icarus_10.md +++ b/bugs/icarus_10.md @@ -1,6 +1,13 @@ # Expression evaluates to 1'bx instead of expected 1'b0 -[ [Issue 283](https://github.com/steveicarus/iverilog/issues/283) ] +[ Not fixed | [Issue 283](https://github.com/steveicarus/iverilog/issues/283) ] + +## Affected versions + +- Icarus Verilog 10.0 +- Icarus Verilog 10.3 + +## Description The following code outputs and assigns `y` to 1'bx instead of 1'b0. This happens in iverilog version 10.3 and also happens in version 10.0 (11/23/14) on edaplayground. However, this seems to execute fine in version 9.6 and 9.7 on edaplayground. @@ -35,4 +42,3 @@ iverilog testbench.v -o im && ./im the output is `x` instead of `0`. If the always block is not used, and the expression is assigned to `y` directly, the result is the expected 1'b0. Any changes to the expression seems to fix the result as well. - -- cgit