From 798f54c05376ec3b4ebbe8326d0a91eec807df3d Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 14 Nov 2019 16:27:19 +0000 Subject: Add proper reports to bugs --- bugs/vivado/1_generated.v | 31 ------------------------------- 1 file changed, 31 deletions(-) delete mode 100644 bugs/vivado/1_generated.v (limited to 'bugs/vivado/1_generated.v') diff --git a/bugs/vivado/1_generated.v b/bugs/vivado/1_generated.v deleted file mode 100644 index de68529..0000000 --- a/bugs/vivado/1_generated.v +++ /dev/null @@ -1,31 +0,0 @@ -// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 -// Date : Thu Apr 11 19:11:05 2019 -// Host : yann-arch running 64-bit unknown -// Command : write_verilog -force syn_vivado.v -// Design : top -// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an -// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input -// design files. -// Device : xc7k70tfbg676-3 -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* use_dsp = "no" *) -(* STRUCTURAL_NETLIST = "yes" *) -module top - (y, - wire0); - output y; - input wire0; - - wire \ ; - wire y; - - GND GND - (.G(\ )); - OBUF y_OBUF_inst - (.I(\ ), - .O(y)); -endmodule -- cgit