From e827635e34079c8ee9c9e7273a59c905274e553d Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 14 Nov 2019 16:49:42 +0000 Subject: Update bug reports --- bugs/vivado_1.md | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'bugs/vivado_1.md') diff --git a/bugs/vivado_1.md b/bugs/vivado_1.md index ef43cdd..3c94ea6 100644 --- a/bugs/vivado_1.md +++ b/bugs/vivado_1.md @@ -1,6 +1,13 @@ # Verilog If statement nesting crash -[ [Vivado forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) ] +[ Not fixed | [Vivado forum 981787](https://forums.xilinx.com/t5/Synthesis/Vivado-2019-1-Verilog-If-statement-nesting-crash/td-p/981787) ] + +## Affected versions + +- Vivado 2019.1 +- Vivado 2018.3 + +## Description The following Verilog code crashes on Vivado 2019.1 and 2018.3. it has been reduced as much as possible to a minimal example from a larger design, which produces the crash. Removing any registers or removing the empty if-statements gets rid of the crash. -- cgit