From 9aced8f8ea480a6aa29acd470857677074bdfd97 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 6 Apr 2019 21:57:13 +0100 Subject: Add more primitives to data/ --- data/cells_yosys.v | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'data/cells_yosys.v') diff --git a/data/cells_yosys.v b/data/cells_yosys.v index 48f9c66..adb8adb 100644 --- a/data/cells_yosys.v +++ b/data/cells_yosys.v @@ -1,13 +1,19 @@ -// Taken from yosys verilog files. +// Taken from yosys simcells.v module \$_DLATCH_N_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = !E ? D : Q; + input E, D; + output reg Q; + always @* begin + if (E == 0) + Q <= D; + end endmodule module \$_DLATCH_P_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = E ? D : Q; + input E, D; + output reg Q; + always @* begin + if (E == 1) + Q <= D; + end endmodule -- cgit