From 8769b3dd59e59d7dd27d726cc125d5bdbd9f096a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 12 May 2019 19:54:29 +0100 Subject: Add FDE cell to xilinx --- data/cells_xilinx_7.v | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'data') diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v index d7e9f67..b4b5467 100644 --- a/data/cells_xilinx_7.v +++ b/data/cells_xilinx_7.v @@ -254,3 +254,14 @@ module LDPE (Q, D, G, GE, PRE); else if (G && GE) Q <= D; endmodule + +module FDE (Q, C, CE, D); + parameter INIT = 1'b0; + output Q; + reg Q; + input C, CE, D; + + always @(posedge C) + if (CE) + Q <= D; +endmodule -- cgit