From c3c561e529b31d6a146621ad7ca2826327a8e87c Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 27 Dec 2018 14:40:54 +0100 Subject: Add another example for declarations in verilog --- examples/decl.v | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 examples/decl.v (limited to 'examples') diff --git a/examples/decl.v b/examples/decl.v new file mode 100644 index 0000000..8f27245 --- /dev/null +++ b/examples/decl.v @@ -0,0 +1,31 @@ +module and_comb(clk, out, in1, in2); + input wire [7:0] in1; + input wire [7:0] in2; + input wire clk; + output reg [7:0] out; + + always @(posedge clk) + begin + out <= in1 & in2; + end +endmodule + +module main; + wire [7:0] c; + reg [7:0] a; + reg [7:0] b; + reg clk; + + and_comb gate(.in1(a), .in2(b), .out(c), .clk(clk)); + + initial + begin + a = 8'd29; + b = 8'd95; + clk = 1'b0; + #10; + clk = 1'b1; + #10 $display("%d & %d = %d", a, b, c); + $finish; + end +endmodule -- cgit